01 — General Description
I'm a digital design and verification engineer working on FPGA and ASIC-class systems. My day-to-day is RTL in SystemVerilog and VHDL, UVM testbenches, and the tooling that keeps large hardware projects sane.
That last part turned into hdlpkg — an open-source package manager and dependency resolver for HDL IP, bringing the ergonomics of cargo, pip and npm to hardware design reuse. I studied at the Universidad Politécnica de Madrid (Digital Architectures & Embedded Systems) and I'm certified in UVM (Doulos) and SystemVerilog (Siemens EDA).
02 — Bill of Materials
A package manager and dependency resolver for HDL IP cores — the ergonomics of cargo/pip/npm, for hardware design reuse.
FEATUREDA microcontroller designed from scratch in VHDL — datapath, control unit and instruction set.
Master's thesis: real-time image filtering accelerated on FPGA fabric.
Bachelor's thesis: electrochemical modeling of Li-ion cells in MATLAB.
A satellite tracking simulator — orbital propagation and ground-station pointing.
Management software for a dry-cleaning business — a full desktop application in C++.
03 — Pin Map
04 — Timing Diagram
ASML · Eindhoven, NL
Digital design and UVM verification for high-tech lithography systems.
Open source
A package manager and dependency resolver for HDL IP cores. → hdlpkg.io
Doulos · Siemens EDA
Professional certification in constrained-random, coverage-driven verification.
Universidad Politécnica de Madrid
Master's thesis: real-time image filtering on FPGA.
Universidad Politécnica de Madrid
Bachelor's thesis: electrochemical modeling of Li-ion batteries.
05 — I/O Ports
Interactive shell — type help and hit enter. Try ls, whoami, neofetch.